An application specific integrated circuit (ASIC) is a custom electronic circuit implemented using VLSI technologies that is designed for a specific application. The circuit of the ASIC is made after designing a hardware circuit in software by inserting and connecting various standardized devices together. The devices include latches, multiplexers, counters and logic gates. The software converts the logical connections to a circuit pattern which can be implemented with the ASIC.
A delay module is available for use in the ASIC circuit to provide a delay of a predetermined amount of time. Methods typically used to make this adjustment to a signal utilize a delay-locked loop (DLL) or a phase-locked loop (PLL).
A DLL consists of a delay module with an adjustable delay time and control logic. The DLL samples an input clock and a feedback clock and determines the appropriate delay time to ensure the input clock and the feedback clock are in phase. It calibrates the adjustable delay time of the delay module accordingly. Once the input clock and the feedback clock are in phase, the DLL locks this delay time into the delay module.
A PLL uses a voltage controlled oscillator whose output phase or frequency locks onto and tracks the phase of the feedback signal. The PLL detects any phase difference between the two signals and generates a correction voltage that is applied to the oscillator to adjust its phase. Some PLLs also allow the output clock to have a 1/N clock period phase shift which provides the fixed time delay.
Use of either of these techniques has disadvantages. The delay time of the DLL varies on the characteristics of the phase comparator. The phase comparator of a DLL would have a limited granularity and its delay time would vary according to variations between circuits on the wafer introduced during the manufacturing process of the wafer, operating voltage and operating temperature for the circuit. A PLL is sensitive to signal variations which requires meticulous layout of its control signals. This sensitivity usually imparts restrictions on the placement of the PLL on the die. This may also limit the number of PLLs that can be placed on the die. Additionally, both a PLL and a DLL require a continuous clock to operate effectively. Gaps or variations in the frequency in the clock signal will cause a PLL or DLL to lose lock.
Many ASIC manufacturers provide in their component library a programmable delay module having an adjustable delay time as an element for an ASIC. Typically, the delay module has an input signal, an output signal and a means for configuring the length of the delay time for the input signal to propagate to the output signal.
A number of factors will cause the delay module in the ASIC to have a delay time in a certain range rather than the desired delay time. This range can be as much as +/−40% from the delay time desired of the delay module. Factors that affect the delay time are variations between circuits on the wafer introduced during the manufacturing process of the wafer (process factors), operating voltage and operating temperature for the ASIC circuit.
Generally, process factors cause the largest variation in delay times. This occurs because each delay module may have variations in deposition sizes for the transistors and interconnections that are used to create the delay module. Increases in voltage and temperature during operation of the ASIC may also lengthen the delay time of the delay module.
There exists a need for a system which addresses the deficiencies of providing accurate times for a delay module for an ASIC.